Questions tagged [chisel]

Chisel is an open-source hardware construction language developed at UC Berkeley that supports advanced hardware design using highly parameterized generators and layered domain-specific hardware languages.

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Using Multiple Clocks in Testers

I have a module with multiple clocks, using withClockAndReset. When writing the testbench, how do I provide a clock stimulus on the named clock port?
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How do you implement active-low reset with named ports?

I'm attempting to use Records along with 'withClockAndReset()' to create an interface Vivado will use, along with the expected negated reset. The approach so far looks like: // Borrowed from https://...
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1answer
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Why doesn't the DspContext work such as withNumAddPipes?

Recently, I have been studying DspContext and type classes in dsptools. I just ran a test code according to the tutorial. It shows how to add pipelines to mathematical operations. But I found this ...
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1answer
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How to writing a accumulator by using ScalaBlackBox?

I want to create some new number types that like DspReal for dsptools, such as DspPosit and DspQuire. DspPosit bases on posit which I have some Java code, and DspQuire bases on quire which is a kind ...
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1answer
52 views

How can I find some manuals about rocket-chip?

I'm learning the code of rocket-chip. But I find it difficult to read its code due to the complex relationship. So I need some maunal to help me. Unluckily, it seems that there are few manuals about ...
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firrtl.Driver is deprecated - but what should we use instead?

I've updated rocket-chip today and noticed that FIRRTL now says this: ------------------------------------------------------------------------------ Warning: firrtl.Driver is deprecated since 1.2! ...
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1answer
49 views

How to duplicate a single bit to a UInt in Chisel 3?

I'm looking for a Chisel way to do the following job: wire [3:0] word; wire bit; assign word = {4{bit}}; I'm currently doing it like this: val word = Wire(UInt(4.W)) val bit = Wire(Bool()) word :=...
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1answer
29 views

What is the purpose of the makeSink method in making IOs for a periphery

I was following some examples of adding peripheries to the rocketchip. I used the sifive-blocks as reference. below is an example from their I2C example (I hope it's ok to post it here) case object ...
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1answer
28 views

declaration and Variable scope in chisel and When block

so I am adding when block around a line in the code but the problem is adding this when block changes the scope making the variables declared inside it not seen from other parts in the program The ...
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1answer
35 views

comparing the value in a register to an int

I am trying to get the value of a reg and compare it with a number inside and if statement val refill_addr = Reg(UInt(width = paddrBits)) if ( refill_addr > 20000.U) cacheable := true ...
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1answer
68 views

Why multiple HCL languages [closed]

I understand that Chisel is a HDL/HCL language to overcome some of Verilog/SystemVerilog restrictions by using higher abstraction level. And it is open source as well. It might be a bit naive and ...
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How to access a sub module register from TestHarness?

I want to change value stored in a rocket core register from the test bench TestHarness.scala. How can I access the register? In TestHarness.scala, I think dut is used to instantiate the ...
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1answer
50 views

Generating Verilog code after BlackBoxing in Chisel3

I am trying BlackBox feature in Chisel3. Every time I try to generate Verilog code of Chisel I got an error. I followed the right steps, writing the class, class driver and build.sbt. I am not sure ...
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1answer
117 views

Simulating a CPU design written in Chisel

I've written a single-cycled CPU in Chisel3 which implements most of the RV32I instructions (except CSR, Fence, ECALL/BREAK, LB/SB, which may be included later). The instructions are currently hard ...
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1answer
38 views

Is there a way to warn wrong clock domain crossing in Chisel3?

As I read from Chisel wiki, it is possible to declare several clock domain in a single module. But if we need to read/write a signal through two different clock domains it's important to manage ...
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2answers
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How to use a chisel3.experimental.ChiselEnum in an I/O port?

Consider this code: import chisel3.experimental.ChiselEnum object MyEnum extends ChiselEnum { val A, B = Value } class UseEnumIO extends Module { val io = IO(new Bundle { val in = Input(...
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1answer
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How to keep all variable name In chisel when generate Verilog code

The Register name in chisel can be definitly found in verilog ,. but Wire name sometimes ellipsis in verilog code. for example , I cant find sjwr ,sjwaddr name in verilog . val sjwr = Wire(...
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1answer
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How do you instanciate a same module twice?

I am developping a code in chisel, and tried to instanciate a module Encryption twice. If I just use Enc0 in the code below, it works fine. But if I use Enc0 and Enc1, then I have the following ...
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How to generate an [error] instead of an [info] upon seeing a wrong value in expect()

Consider the following code: import chisel3._ import chisel3.util._ import chisel3.iotesters._ class Inverter extends Module { val io = IO(new Bundle { val a = Input(UInt(4.W)) val s = ...
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1answer
40 views

Chisel3: How to create a register without reset signal in RawModule?

I want to create a RegNext in a RawModule, with the help of withClock. However, it can't work while the error information shows that missing implicit reset. So I have to write it like this: class ...
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0answers
63 views

Vivado can't recognize the double-port RAM while using SyncReadMem

I want to create a true double-port RAM in Chisel and synthesize the Verilog code in Vivado 2018.3. Here is my Chisel code: class DoublePortsRAM extends Module { val io = IO(new Bundle { val ...
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2answers
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What mechanism works to show component ID in chisel3 elaboration

Chisel throws an exception with an elaboration error message. The following is a result of my code as an example. chisel3.core.Binding$ExpectedHardwareException: data to be connected 'chisel3.core....
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For loop representation in Chisel (@Normalization in Float Adder)

I try to code floating adder; https://github.com/ElectronNest/FPU/blob/master/FloatAdd.scala This is half way. The normalization is huge code part, so I would like to use for-loop or some equivalent ...
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2answers
60 views

Chisel how to test only one package

I am working with chisel-template In my src/main/scala I have two folders, let say A and B. In src/test/scala, I have a folder for A and a folder for B. I want to test only A but when I do $ sbt ...
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1answer
297 views

java.lang.AssertionError: assertion failed:

[error] (run-main-0) java.lang.AssertionError: assertion failed: [error] java.lang.AssertionError: assertion failed: [error] at scala.Predef$.assert(Predef.scala:170) [error] at chisel3.core....
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1answer
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Not sign-extended in AND operation in firrtl

I tried a simple test like below in chisel3. import chisel3.iotesters.{ChiselFlatSpec, Driver, PeekPokeTester} import chisel3._ class TestTesterUnit(c: Test) extends PeekPokeTester(c) { val value =...
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1answer
27 views

Generic Address Decoder

I'd like to implement a generic addr decoder. This is a follow up question to this post. class AddrDecoder[T <: Data with Num[T]] (dType:T, n:Int) extends Module { val io = IO (new Bundle { ...
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1answer
80 views

Why does implicit type conversion from Int to UInt not work?

I'm trying to learn chisel3, and I also try to be able to use implicit type conversion from Int to UInt in specific case. Following is my code. package VecTest import chisel3._ import scala....
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2answers
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Type Class for Complex Numbers

I need to implement a custom type class for Complex DSP and Complex Ring operations. I'm aware about DspTools project, but purposely want to exclude it from consideration. I've got a hardware module, ...
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1answer
37 views

Conditional Bulk Connection <>

I would like to do a conditional bulk connection of bidirectional buses, conceptually like the following. val io = IO(new Bundle { val master = Decoupled(UInt(8.W)) val slave0 = Flipped(Decoupled(...
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1answer
28 views

How to get the PeekPokeTester expect function to print signal values in hex?

By default when I call the expect() function in the tester the values come up as decimals. Although in the provided example here: https://github.com/freechipsproject/chisel-testers/wiki/Using-the-...
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1answer
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Compiling Modules Separately and Linking

I'm compiling some very large projects in chisel3 with lots of wires and connections. Right now, the top level object and all of its submodules are in the same Scala package, and I run sbt "runMain ...
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1answer
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How to replace combinational memory with ASIC cell in Chisel

I am trying to do ASIC synthesis for Rocket processor which is written by Chisel. It automatically generates *.conf and *.behave_srams.v files. So, I can easily replace SeqMem with ASIC SRAM. However, ...
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1answer
54 views

How to iterate through similar registers definition in Chisel (regmap)

I have some similar register definition, and I want to write under the regmap construct. My code currently looks like this: val regs = RegInit(Vec(Seq.fill(5)(0.U(32.W)))) regmap ( ... 0x30 -> ...
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1answer
28 views

Testing a DSPComplex ROM

I'm working on building a DSPComplex ROM still and have hit what I think may be an actual Chisel problem. I've built the ROM, can generate a verilog output from the code that looks reasonable, but ...
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Changing clocking in RocketSubsystemModuleImp from System.scala

I'm trying to alter the clocks and resets which go to each Rocket tile in my system. At the moment I'm trying to do it like this. In Platform.scala I have some inputs declared in my PlatformIO (where ...
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1answer
64 views

How to use experimental features in Chisel3?

I wanted to load a memory from file using functions described in this chisel wiki page. But it's an experimental feature, and the import command : import chisel3.util.experimental.loadMemoryFromFile ...
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1answer
43 views

Building a DspComplex ROM in Chisel

I'm attempting to build a ROM-based Window function using DSPComplex and FixedPoint types, but seem to keep running into the following error: chisel3.core.Binding$ExpectedHardwareException: vec ...
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1answer
40 views

Chisel testbenches: controlling multiple ports independently

I have a module with multiple DecoupledIO inputs and outputs. Is there a way to supply stimuli and gather responses to/from each port independently? I can "emulate" this behaviour in a PeekPokeTest ...
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33 views

How does scratchpad works in rocketcore icache?

It is confusing to me the role of scratchpad in icache in the rocket core. Could anyone help explain it?
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2answers
257 views

Any way to work around JVM code size limits tripped by large Chisel file

Just say you were autogenerating some Chisel code for some infrastructure in your chip. A single file instantiating a load of memory mapped registers and then IO assignments. Then say one day you add ...
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48 views

How do Rocket Core icache/dcache interact with DRAM?

I am trying to make some modifications to Rocket Core memory system, but I have difficulty finding how rocket core (icache/dcache) interacts with the DRAM. Could anyone help explain how are they ...
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2answers
125 views

How to printf or println UInt in chisel?

I am trying to execute the following code: val num1 = 10.U printf(p"num1 = $num1") I am getting the following error when running this code in an example class. [error] (run-main-8) chisel3.internal....
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1answer
61 views

How to generate Verilog code with parametized modules in Chisel?

The following module definition in chisel: class Mux2 (width: Int = 4) extends Module does not result in a Verilog module that is parametrized. The generated Verilog RTL will instead substitute the ...
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1answer
51 views

How to decipher comments in generated Verilog from chisel?

Here is some genereated Verilog from the PassTrough module found in: https://github.com/freechipsproject/chisel-bootcamp/blob/master/2.1_first_module.ipynb module PassTrough( // @[:@3.2] input ...
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1answer
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How to import getVerilog() function from the bootcamp examples?

I am not sure I understand how to use the getVerilog function from: https://github.com/freechipsproject/chisel-bootcamp/blob/master/2.1_first_module.ipynb [error] passthrough_test.scala:18:11: not ...
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1answer
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what is “wxd” in rocketcore?

In the rocket core bypass logic val bypass_sources = IndexedSeq( (Bool(true), UInt(0), UInt(0)), // treat reading x0 as a bypass (ex_reg_valid && ex_ctrl.wxd, ex_waddr, mem_reg_wdata), (...
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2answers
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How to make assertions in Chisel be just warnings and not stop simulation

We have added assertions to our Chisel code, but we only want them to warn, not stop the simulation. Is there a way to tell Chisel to do this? For example: assert(x(1) =/= nxt_val(1)) We want this ...
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0answers
50 views

How do I run a single UnitTest from rocket-chip?

Specifically I'd like to run AXI4XbarTest from rocket-chip/src/main/scala/amba/axi4/Xbar.scala. It looks this test should be run by the regression tests, but if I go into the regression directory and ...
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How to derive rising and falling clock events?

For a clocked Wire, I'd normally do the following: val gntRisingEdge = gnt && ~RegNext(gnt) However, I can't do the same for the Clock signal, since RegNext(gnt) is updated only after the ...